Freescale Semiconductor /MK70F12 /DDR /CR05

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR05

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TWTR0TRP0TRTP0TMRD

Description

DDR Control Register 5

Fields

TWTR

Time Write-To-Read

TRP

Defines the DRAM precharge command time (TRP) in cycles.

TRTP

Time Read-To-Precharge

TMRD

DRAM TMRD parameter in cycles.

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